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DACS: Timing and Levels
 
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Timing and Levels

The Pbus is a relatively low-speed digital I/O bus. Timing is not exceptionally critical, as the speed of the bus is in the sub-1MHz range. Nevertheless, a visual reference to the bus timings is useful to fully understand the Pbus . Figure 35 depicts the timing for the Pbus master reading data from a slave device. Figure 36 shows the timing for the Pbus master writing data to a slave.

Figure 35: Pbus timing diagram for input (Pbus master reading slave).
\begin{figure}
\psfig{file=fig/pbus-time-in.eps,width=6in}
\end{figure}

Figure 36: Pbus timing diagram for output (Pbus master writing to slave).
\begin{figure}
\psfig{file=fig/pbus-time-out.eps,width=6in}
\end{figure}

Note that the control signals of the bus are level-sensitive, not edge-triggered. During the time when a particular input or output window is active, there is a transparent window between the master and the active slave(s), in the direction dictated by the direction control line.

Steve Richardson 2000-07-06
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